Pipelined Heap ( Priority Queue ) Management for AdvancedScheduling in High - Speed

Per-ow queueing with sophisticated scheduling is a candidate architecture for networks that provide advanced Quality-of-Service (QoS) guarantees. The hardest and most interesting scheduling algorithms rely on a common computational primitive: priority queues. Large priority queues are built using calendar queue or heap data structures. To support such scheduling for a large number of ows at OC-192 (10 Gbps) rates and beyond, pipelined management of the priority queue is needed. We present heap management algorithms that can be gracefully pipelined; they constitute modiications of the traditional ones. We discuss how to use a pipelined heap manager in switches and routers, its advantages over calendar queues, its structure and its cost-performance tradeoos. The design can be conngured to any heap size, and, using 2-port 4-wide SRAM's, it can support initiating a new operation on every clock cycle, except that an insert operation or one idle (bubble) cycle is needed between two successive delete operations. We present a pipelined heap manager implemented in synthesizable Verilog form, as a core integratable into ASIC's. We have veriied our design by co-simulating it with three heap models of varying abstraction. We have also performed synthesis, and present cost and performance analysis information. For a 16K entry example in 0.18-micron CMOS technology, silicon area is approximately 15mm 2 and performance is a few hundreds of millions operations per second.